“Azuro’s proprietary global approach to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, chief executive officer and co-founder of Azuro. “PowerCentric is being actively used to tapeout many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”
Key features in PowerCentric version 5 include:
– 30% reduction in CTS runtimes on designs with multiple modes and corners
– Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10% additional clock power savings
– Comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format
– The new Trial CTS capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances
– Top level clock balancing through hardened sub-chips with back-annotated parasitics
– Full database save with rapid restore
PowerCentric version 5 is available now with UPF 2.0 support in limited availability.
