The 65nm low leakage process IPs also includes the preliminary version release of six memory compliers. This portfolio, which consists of number of new, ready-to-use IPs, follows the 65nm standard cell libraries that were released in earlier 2009.
The centerpiece of SMIC’ s new 65nm IP offerings is the set of six memory compilers, which allows the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers include memories optimized for very high performance and also optimized for performance and area. These critical IPs, along with many others in the portfolio, were developed internally by SMIC’s design services group with rigid design methodology. The silicon validation is undergoing.
Because SMIC’s 65nm library was developed in-house, it provides customers a number of advantages in flexibility and customizability, enabling for the library to be easily tuned to processes and recharacterized according to customer requests, streamlining the design flow and improving time to market.
“This 65nm IP portfolio are targeting both low power and high speed applications, allowing customers to come in and start designing a wide range of system-on-chip projects,” said Paul Ouyang, SMIC’s vice president of design services, adding that the company has already engaged a number of customers in the 65nm node. “The set of memory compilers is a full-featured high quality product, and this accomplishment is a testament to the talented and dedicated engineers in SMIC’s design services group.” Scheduled production release of the memory compilers will be on June 30, 2008. Additional in-house and third party 65nm IPs are under development, which are planned to be available to customers later 2009.
SMIC is a China-based company.
