For designers and the signal integrity engineers working with high speed semiconductor devices, these new instruments help improve the development costs and time to market by speeding up troubleshooting and the compliance testing.
The 17500C model includes wide capabilities for performing jitter and interference tolerance testing as needed by many standards. It also has the new Jitter Map functionality. This is a first in the industry with its ability to perform the detailed jitter analysis on long patterns and also the more usual short patterns.
The BERTScope Si 17500C also has improved integrated stress generation beyond the standard stresses available in BERTScope S, extended to 17.5 Gb/s.
Sinusoidal Jitter (SJ) amplitudes at the jitter frequencies less than 160 kHz have been greatly increased. Jitter tolerance SJ requirements met or exceeded include: SONET/SDH OC-192/STM-64, Fibre Channel, Xaui, 10 GBASE-R, and XFP;
F/2 jitter, which varies the pulse widths of odd vs. even bits in data pattern, is added for 10 GBASE-KR and the general purpose usage up to 11.2 Gb/s;
Spread Spectrum Clocking (SSC) on the data rates from 500 Mb/s to 17.5 GB/s. SSC can be used simultaneously with SJ and other stresses.
